LUMA · TECHNICAL PARTNER EXECUTION

Know your input. Own your artifact. Hand it to the next block.

LUMA is a 36-month hardware-software research programme built around one measurable chain: a defined inference service becomes a physically qualified machine state, then progressively stronger compute, memory, control and integration mechanisms are accepted only when they improve the same service/resource boundary.

Implementation baselineRTL / FPGA + physical integration. No mandatory tapeout dependency.
TASK-LEVEL ARTIFACT CHAIN

Every block receives a named artifact and returns a named artifact.

The consortium PDF carries the full task register. This public-safe view shows the same technical direction without partner budgets, private repository paths or unconfirmed institutional commitments.

WP1 · CHARACTERIZE

Service → WCR-compute / WCR-memory / WCR-node → R1

Compound Pulse freezes model, workload, quality/SLO and economics. The compute-characterization lane returns operation/precision/expert/state demand; the memory lane returns traffic/reuse/bandwidth constraints; the physical-backend lane returns measured FPGA-node bandwidth, latency, power and toolchain evidence.

NEXT → WP2 mechanism teams + WP3 backend/control
WP2 · BUILD MECHANISMS

R1 → buildable compute/memory packages

Mechanism owners return bounded low-bit/MoE, sparse/event-driven, near-memory or configurable compute packages. Each package carries executable RTL/HLS or an implementation-ready architecture, golden tests, interface/state map, build constraints and QoR evidence.

NEXT → physical backend build/run; DFX transition framework where persona-compatible; runtime-control descriptors; Compound Pulse qualification
WP3 · EXECUTE + SWITCH

Qualified candidate → controller + DFX + immutable physical FPGA evidence

The runtime-control lane applies, observes, verifies and retains or rolls back. The DFX lane owns state-safe partial reconfiguration. The physical-backend lane owns admitted FPGA build/run and synchronized timing, bandwidth, latency, power, temperature and service evidence.

NEXT → Compound Pulse same-service qualification + measured corrective feedback
WP4 · PHYSICALIZE

Qualified endpoint → PITV + Taiwan implementation artifact

The physical-integration lane converts endpoint traffic, clock, power and interface requirements into PITV/SI/PI/PDN/thermal evidence. A semiconductor/implementation lane returns a named target/toolchain artifact with timing, resources/PPA, power and reproducibility.

NEXT → WP5 integrated qualification
WP5 · QUALIFY + CORRECT

Integrated artifacts → same-service RBR + owner-specific corrective loop

Compound Pulse closes TTFT/TPOT, accepted goodput, device/server provision, wall power, J/accepted output and cost/accepted output. A failed gate returns only to the responsible result owner with the measured deficit.

NEXT → accepted state to WP6; rejected state to its named owner
WP6 · RELEASE

Accepted states → customer/operator release + exploitation

Compound Pulse integrates the deployable bundle and Resource Boundary Report. Technical partners contribute only the foreground and reproducibility package for the artifact they own; there is no generic all-partners WP6 task.

NEXT → customer/operator/design partner + evidence-based post-project hardening decision
COMMON PARTNER INTERFACE

Every partner contract uses the same five fields.

01FROM WHOM

Named upstream team and exact artifact/version you receive.

02YOU OWN

One bounded technical task with a hands-on builder and a 36-month sequence.

03YOU RETURN

Executable or physical artifact, evidence record and reproducibility material.

04TO WHOM

Named downstream team that consumes your output and the interface it expects.

05ACCEPTANCE

Measured FOMs that connect the artifact to accepted service, energy, resource provision or cost.

36-MONTH RESEARCH PROGRESSION

Successive technical generations, not a Year-1 finish.

The M12 customer gate is a defined physical/software bundle, while the RIA remains technically active through M36.

M1-6Explore + characterize

Workload cells, node profiles, early physical-interface exploration, first architecture decisions and R1-v0.

M7-12Fixed-FPGA Customer Qualification

First RTL/PIM/persona implementations; one qualified FPGA backend path; L0 apply/observe/verify; synchronized service/power evidence; first RBR.

M13-18Adaptive DFX Qualification

Second mechanism generation; at least two qualified paths; state-safe A↔B DFX; measured switch cost, rollback and service continuity.

M19-24Physical iteration

PITV/board integration, power/thermal/interface evidence and corrective technical iteration.

M25-30Cross-Backend TRL4 Candidate

Broader workloads, recovery stress, second backend and repeated integrated evidence.

M31-36Final TRL4 / Reproducibility Transfer

Final reproducibility, TRL4 evidence, customer/operator release and result-owner handoffs.

CONTROLLED TECHNICAL ACCESS

Common context first. Role-scoped disclosure second.

The public execution model is intentionally role-based. Exact workload traces, R1 records, test vectors, source modules and black-box specifications move only after institutional confidentiality/cooperation alignment and are limited to the recipient's role.

Common pack

Public execution model + current programme roadmap + your role-specific interface summary.

After NDA

Exact role inputs, test vectors, backend/interface records and relevant source modules.

Evidence return

Artifact identity, tool/build provenance, measured FOMs, acceptance result and downstream handoff.

Adaptive FPGA truth: LUMA may switch automatically among prebuilt, physically qualified FPGA personas. New persona generation, synthesis, place-and-route and qualification occur offline before a persona enters that runtime library.
LUMA · TECHNICAL EXECUTION

One role. One artifact. One measurable handoff.

Emmanuel Dessallien · ed@compound-pulse.com